Design of LDPC Decoders for Low Error Rate Performance

Many classes of high-performance low-density parity-check (LDPC) codes are based on parity check matrices composed of permutation submatrices. We describe the design of a parallel-serial decoder architecture that can be used to map any LDPC code with such structure to a hardware emulation platform. High-throughput emulation allows for the exploration of the low bit error rate (BER) region and provides statistics of the error traces, which illuminate the causes of the error floors of the (2048,1723) Reed-Solomon based LDPC (RS-LDPC) code and the (2209,1978) array-based LDPC code. Two classes of error events are observed: oscillatory behavior and convergence to a class of non-codewords, termed absorbing sets. The influence of absorbing sets can be exacerbated by message quantization and decoder implementation. In particular, quantization and function estimation strongly affect which absorbing sets dominate in the error floor region. We show that conventional sum-product decoder implementations of the (2209,1978) array-based LDPC code allow low-weight absorbing sets to have a strong effect, and, as a result, elevate the error floor. Adaptively-quantized sum-product decoders and approximate sum-product decoders alleviate the effects of low-weight absorbing sets, thereby lowering the error floor. Index Terms – low-density parity-check (LDPC) code, message passing decoding, iterative decoder implementation, error floor, absorbing set.